1. Field of the Disclosure
The present disclosure relates generally to memory devices and more particularly to die-stacked memory devices.
2. Description of the Related Art
Processing systems generally implement system memory as a device separate from the devices implementing processors, input/output (I/O) components, and other components. Such systems therefore are often bandwidth-limited due to the volume of traffic on the interconnect connecting the system memory to the other components and latency-limited due to the propagation delay of the signaling traversing the relatively-long interconnect and due to the handshaking process needed to conduct such signaling. The inter-device bandwidth and inter-device latency have a particular impact on processing efficiency and power consumption for data translation operations. To perform a data translation operation, a system component typically accesses data from the system memory, transforms the data, and then stores the translated data back to the system memory. As such, each data translation often involves at least two memory accesses, and thus the inter-device bandwidth and latency penalties are incurred twice for each data translation. Moreover, these bandwidth and latency issues are compounded by the fact that many data translation operations involve numerous data translations.